The present invention relates to a semiconductor device in which a capacitive element, a resistor and a transistor are provided.
The (analog-digital) semiconductor device in which a capacitive element and a resistive element are provided in addition to a MOS transistor according to the prior art has been implemented by adding the steps of manufacturing the capacitive element and the resistive element (analog) to the steps of manufacturing an ordinary MOS transistor (digital). In this case, it is desirable that a capacitive element having a great capacitance value per unit area should be formed in order to reduce the area occupied by the capacitive element.
The structure and manufacturing steps of a semiconductor device in which the MOS transistor and a two-layer polysilicon type capacitive element are provided according to the prior art will be described below. FIGS. 8(a) to 8(d) are sectional views showing the manufacturing steps of a semiconductor device in which an n-channel type MOS transistor and a two-layer polysilicon type capacitive element are provided.
As shown in FIG. 8(a), a LOCOS isolation 102 is formed on a part of a p well 101 of a silicon substrate. A region where the surface of the p well 101 is exposed is a region Rtra where a transistor is to be formed. A region Rcap where a capacitive element is to be formed is provided on the LOCOS isolation 102.
As shown in FIG. 8(b), a polysilicon film is deposited in a thickness of 200 nm, for example. Then, a first conductor film into which an impurity is introduced (not shown) by a POCl.sub.3 diffusion method or the like is deposited to form a first resist film 104 having a desired pattern. Thereafter, the first conductor film is patterned by a dry etching method to form a lower capacitive electrode 103a.
As shown in FIG. 8(c), a gate oxide film 105 is formed by pyrogenic oxidation in a thickness of 10 nm, for example. At this time, an oxide film is simultaneously formed on the lower capacitive electrode 103a in a thickness of about 20 nm to be a capacitive film 106 (which has a greater thickness than that of the gate oxide film 105 because polysilicon is oxidized more quickly than single crystal silicon). Then, a second conductor film (not shown) made of a polysilicon film having a thickness which is almost the same as that of a first conductor film 103a is formed on the LOCOS isolation 102, the gate oxide film 105 and the capacitive film 106. Consequently, a second resist film 109 having a desired pattern is formed on the second conductor film. By using the second resist film 109 which covers a part of the region Rtra and a part of the first conductor film 103a of the region Rcap, a second conductor film is patterned by the dry etching method to form a gate electrode 107a in the region Rtra and an upper capacitive electrode 107b on the capacitive film 106 in the region Rcap, respectively.
As shown in FIG. 8(d), an n-type impurity is introduced into the p well 101 to form a source-drain region. Then, a layer insulating film 113, a contact hole 114 and a metal wiring layer 115 are successively formed. Thus, a semiconductor device in which the n-channel transistor and the two-layer polysilicon type capacitive element are provided is manufactured.
However, the capacitive film of the capacitive element is formed at the steps shown in FIGS. 8(a) to 8(d) simultaneously with the formation of the gate oxide film of the MOS transistor. For this reason, the capacitance value per unit area is defined by the material and the thickness of the gate oxide film. Since the capacitance value per unit area of the silicon oxide film is small, it is difficult to increase only the capacitance value per unit area of the capacitive film of the capacitive element. In addition, the capacitive film is formed by the oxidation of the polysilicon. The speed at which the polysilicon is oxidized is higher than the speed at which a silicon single crystal is oxidized. Consequently, the thickness of the capacitive film is much greater than that of the gate oxide film. Accordingly, the capacitance value per unit area of the capacitive film becomes small. For this reason, it is difficult to reduce the occupied area.
Also in the case where two-layer polysilicon is used, the gate oxide film and the capacitive film of the capacitive element can be formed of an insulating film having a different material as a method other than the method shown in FIGS. 8(a) to 8(d). In this case, a silicon nitride film which is separately deposited in place of the oxide film is patterned to be the capacitive film 106 in the state shown in FIG. 8(c). At this time, the capacitance value per unit area is not defined by the material and the thickness of the gate oxide film. Consequently, it is possible to reduce the occupied area. However, it is necessary to separately add the step of forming an etching mask for patterning the silicon nitride film. For this reason, the number of manufacturing steps is increased so that the whole manufacturing cost is raised.
As a variant of the above-mentioned method, there is also a method in which a gate oxide film is formed, a conductor film is deposited as the gate electrode of a transistor and the lower capacitive electrode of a capacitive element, and a silicon nitride film or the like is formed on the conductor film. A conductor film on which a silicide film having a low resistance is laminated is used for the gate electrode. However, in the case where the silicide film or the like is used for the lower capacitive electrode, the voltage withstanding properties and the reliability of the capacitive film formed on the lower capacitive electrode are deteriorated. It is also considered that a silicon nitride film or the like is deposited on the first conductor film 103a in advance in the state shown in FIG. 8(b). In this case, the silicon nitride film is oxidized when forming the gate oxide film. Consequently, the capacitance value per unit area of the capacitive film is finally reduced.
Furthermore, the following method has also been known well. More specifically, a surface concentration in the vicinity of the gate oxide film of a well of a MOS transistor is controlled to form a MOS transistor of a depression type and a capacitive element made of the gate oxide film is formed simultaneously. In this method, the number of manufacturing steps is hardly increased. However, the capacitance value per unit area is comparatively small so that the area occupied by the capacitive element is increased. Consequently, it is hard to obtain high integration. In addition, the voltage dependency of the capacitance value is increased. For this reason, it is impossible to obtain the precision necessary for the use in an analog circuit.
As described above, the above-mentioned methods have merits and demerits. A device which can meet general requirements such as quality, a reduction in the area and manufacturing cost has not been made for practical use. Also in an analog-digital LSI, more fineness and higher integration have been demanded. Referring to an analog portion, the process for effectively reducing the area and the number of manufacturing steps at the same time has not been proposed and should be developed in order to realize the integration of the analog-digital LSI.
In the prior art, a resistive element is formed of a conductor film (a sheet resistance of 30 to 100.OMEGA./.quadrature.) which is obtained by introducing an impurity into polysilicon by the POCl.sub.3 diffusion method or an ion implantation method. A conductor film having a low resistance (a sheet resistance of 5 to 10.OMEGA./.quadrature.) such as polycide which is formed by a lamination of polysilicon and silicide has been used for a gate electrode in such a manner that it can also be used for a local wiring. However, in the case where a certain resistance value is obtained in the resistive element, a conductor film having a comparatively high resistance value should be used as a resistive film in order to reduce the area of the resistive element. For this reason, it is necessary to form a conductor film as the gate electrode by using a material having a low resistance and to form a conductor film as the resistive film by using a material having a comparatively high resistance without increasing the number of steps.